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Features
* Interfaces Directly to Instrument Hardware
- Keyboard Velocity Scanner (Up to 88 Keys, 64 s Time Accuracy, Log Timescale) - Switch Scanner (Up to 176 Switches) - LED Display Controller (Up to 88 LEDs) - Slider Scanner (Built-in ADC, Up to 16 Sliders) - LCD Display (8-bit Interface) Crisp Musical Response - 45 MHz Built-in 16-bit Microcontroller - Interface with Keyboard/Switches through Built-in Shared Memory High-quality Sound - 64-slot Digital Sound Synthesizer/Processor - Multi-algorithm: PCM with Dynamic LP Filter, FM, Delay Lines for Effects, Equalizer, Surround, Digital Audio-in Processing - Compatible with SAM97xx Sounds and Firmware - 44.1 kHz Sampling Rate - Up to 16 MB x 16 ROM/RAM for Firmware, Orchestration and PCM Data - Up to 4 Channels Audio-out, 2 Channels Audio-in Top Technology - 144-lead TQFP Space-saving Package - Single 11.2896 MHz Crystal Operation, Built-in PLL Minimizes RFI Available Soundbanks for General Midi(R)(GM)(1)or High-quality Piano - CleanWave(R) 1-Mbyte and 4-Mbyte Sample Sets (Free License) - High-quality 2-Mbyte Piano and Strings Sample Sets - Other Sample Sets Available Under Special Licensing Conditions Quick Time-to-market - Proven Reliable Synthesis Drivers - In-circuit Emulation with CodeView Debugger for Easy Prototype Development - Built-in External Flash Programming Algorithm, Allows On-board Flash Programming - All Existing SAM97xx Tools Available for Sound and Sound-bank Development 1. General MIDI requires a license from Midi Manufacturers Association.
* *
Integrated Digital Music Instrument SAM9753
* *
*
Note:
Description
The SAM9753 integrates a SAM97xx core (64-slot DSP and 16-bit processor), a 32K x 16 RAM, an LCD display interface and a scanner into a single chip, allowing direct connection to velocity-sensitive keyboards, switches, LEDs and sliders. With the addition of a single external ROM or Flash and a stereo DAC, a complete low-cost musical instrument can be built that includes reverb and chorus effects, parametric equalizer, surround effects, orchestrations, pitch-bend and wheel controller, without compromising on sound quality. The SAM9753 is packaged in a standard 144-lead TQFP package.
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Figure 1. Typical Application for the SAM9753
ROM
Keyboards Switches LEDs LCD Display Sliders MIDI IN/OUT
SAM9753
DAC
Figure 2. SAM9753 Block Diagram
DACLK DABDx DAAD CLBD WSBD RUN 32K x 16 SRAM Memory Management Unit
64-slot DSP with Algorithms in RAM
P16 Processor 256 x 16 RAM 512 x 16 ROM
A0 - A23 D0 - D15 RD, WR CSx XIOx MIDI IN/OUT GPIO0 - GPIO4
DEBUG
MIDI UART 3 x Timers Control and Status Regs
X1, X2 LFT RESET PDWN Clock and PLL
128 x 16 Scanning RAM
Keyboards Switches Sliders LEDs Scanning I/F
KBD1IO ROW0 - ROW2 BR0 - BR10 MK0 - MK10 8-bit ADC VREFP VREFN VIN
LCD Display Interface
DB0 - DB7 RS R/W E
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Table 1. Pin Description by Function
Pin Name Pin Number Type Function Power Supply(1) GND 4, 17, 24, 32, 42, 52, 56, 65, 77, 90, 97, 102, 110, 125, 130, 140 103 5, 18, 31, 41, 51, 66, 78, 91, 111, 126, 139 23, 55, 96, 101, 129 107 PWR Digital Ground All pins should be connected to a ground plane. Analog Ground for the ADC Power Supply, 3.3V/5V 10% All pins should be connected to a VCC plane. Core power, +3.3V nominal (3.3V 10%). All VC3 pins should be returned to +3.3V. Analog power for the ADC, +3.3V nominal (3.3V 10%) Serial MIDI MIDIIN MIDIOUT 94 95 IN OUT Serial MIDI IN Serial MIDI OUT
AGND VCC VC3 AVC3
PWR PWR PWR PWR
External PCM ROM/RAM/I/O WA0 - WA23 WD0 - WD15 RD WR CS0 - CS1 XIO0 - XIO1 47 - 50, 53, 54, 57 - 64, 67 - 76 19 - 22, 25 - 30, 33 - 38 39 40 43, 44 45, 46 OUT I/O OUT OUT OUT OUT External memory I/O address. Up to 16M x 16 for direct ROM/RAM connection. External memory I/O data. Data is read (input) when RD is low, written (output) when WR is low. External ROM/RAM/peripherals read External RAM/peripherals write Programmable chip selects. Can be configured to handle several ROMs or mixed RAM/ROM/FLASH. External peripherals chip select. Each peripheral maps onto 4K bytes address space for optional further decoding.
Keyboard, Switches, LEDs, Sliders, Scanning KBDIO ROW0 - ROW2 119 115 - 117 OUT OUT If 1: BR[0:10] and MK[0:10] hold keyboard contact input data. If 0: BR[0:10] holds switch status input, MK[0:10] holds LED data output. Row select: Keyboard, switches/LEDs, external slider analog multiplexer (4051) channel select. Eight rows combined with eleven BR/MK columns allow to control 88 keys, 88 switches, 88 LEDs and 8 sliders. The programmable bit GPIO0 allows control to be extended to 176 switches and 16 sliders when programmed as ROW3. Keyboard contact 1/switch status. When KBDIO = 1 then BR[0:10] holds the keyboard key-off or first contact status. This can be configured as normally closed (spring type), normally open (rubber type), common anode or common cathode contact diodes. When KBDIO = 0 then BR[0:10] holds the switch status from ROW[0:2] or ROW[0:3].
BR0 - BR10
1 - 3, 135 - 138, 141 - 144
IN
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Table 1. Pin Description by Function (Continued)
Pin Name MK0 - MK10 Pin Number 120 - 124,127, 128, 131 - 134 Type I/O Function Keyboard contact 2/LED data. When KBDIO =1 then MK[0:10] holds the keyboard key-on or second contact status. This can be configured as common anode or common cathode contact diodes.When KBDIO = 1 then MK[0:10] holds the led data from ROW[0:2]. Positive reference voltage. Should normally be connected to a clean AVC3 supply. Negative reference voltage. Should normally be connected to a clean AGND. Slider analog input. Ranges from VREFN to VREFP. Should hold the ROW[0:2] or ROW[0:3] slider voltage. Multiple sliders should be connected through external analog multiplexer(s) like 4051. LCD Display Interface(2) RS RW ENB DB0 - DB7 16 15 14 6 - 13 OUT OUT OUT I/O Select instruction (LOW) or data (HIGH). Select write (LOW) or read (HIGH). Enable, active high. Bi-directional data bus. Digital Audio Group(3) DACLK DABD0 - DABD1 DAAD CLBD WSBD 93 89, 92 88 86 87 OUT OUT IN OUT OUT Master clock for sigma-delta DAC (256 x Fs). Serial data for two stereo output channels. Serial data for one stereo input channel. Digital audio bit clock. Digital audio left/right select. Miscellaneous Pins GPIO0 - GPIO4 108, 109, 112 - 114 I/O These pins can be used individually as general-purpose I/Os or as alternate functions. When used as general-purpose I/Os, they can be individually configured as inputs or outputs. When used as alternate functions their meaning changes as follows: GPIO0 = ROW3 expands switches to 176, sliders to 16 GPIO1 = RAMCS GPIO2 = DBCLK (input) GPIO3 = DBACK (output) GPIO4 = DBDATA (I/O) DBCLK, DBACK, DBDATA are used for debugging or external Flash memory programming when DEBUG is low Configuration pin, low for CodeView debugging/external Flash memory programming. Should be tied to VCC for normal operation. Reset input, active low. This is a Schmitt trigger input, allowing direct connection of a RC network. Indicates that the DSP is up and running. Can be used as external DAC reset. Power down, active low. When power down is active, all output pins are floating except GPIO1. The crystal oscillator is stopped. To exit from powerdown mode, PDWN should be high and RESET applied.
VREFP VREFN VIN
106 105 104
ANA ANA ANA
DEBUG RESET RUN PDWN
85 83 118 84
IN IN OUT IN
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Table 1. Pin Description by Function (Continued)
Pin Name X1 - X2 TEST0 - TEST3 LFT Notes: Pin Number 98, 99 79 - 82 100 Type - IN - Function 11.2896 MHz (nominal) crystal connection. An external clock can also be used at X1. Test pins, should be grounded PLL external RC network
1. Like all high-speed HCMOS ICs proper decoupling is mandatory for reliable operation and RFI reduction. The recommended decoupling is 100 nF at each corner of the IC with an additional 10 F bulk capacitor close to the X1, X2 pins. 2. The LCD display interface signals are controlled by firmware, therefore, their timing relationship is determined by firmware only. 3. The SAM9753 connects to a variety of stereo DACs or Codecs from 16 to 20 bits, with Japanese or I2S format. This includes AD1857JRS, PCM1718, PCM3001, TDA1305, TDA1543, TDA1545, TDA1311. When Japanese format is used, only 16 bits is supported without external circuitry.
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Table 2. Pinout by Pin Number
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name BR8 BR9 BR10 GND VCC DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ENB RW RS GND VCC WD15 WD14 WD13 WD12 VC3 GND WD11 WD10 WD9 WD8 WD7 WD6 VCC GND WD5 WD4 WD3 WD2 Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name WD1 WD0 RD WR VCC GND CS1 CS0 XIO1 XIO0 WA23 WA22 WA21 WA20 VCC GND WA19 WA18 VC3 GND WA17 WA16 WA15 WA14 WA13 WA12 WA11 WA10 GND VCC WA9 WA8 WA7 WA6 WA5 WA4 Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin Name WA3 WA2 WA1 WA0 GND VCC TEST0 TEST1 TEST2 TEST3 RESET PDWN DEBUG CLBD WSBD DAAD DABD0 GND VCC DABD1 DACLK MIDIIN MIDIOUT VC3 GND X1 X2 LFT VC3 GND AGND VIN VREFN VREFP AVC3 GPIO0 Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Pin Name GPIO1 GND VCC GPIO2 GPIO3 GPIO4 ROW0 ROW1 ROW2 RUN KBDIO MK10 MK9 MK8 MK7 MK6 GND VCC MK5 MK4 VC3 GND MK3 MK2 MK1 MK0 BR0 BR1 BR2 BR3 VCC GND BR4 BR5 BR6 BR7
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Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings (All Voltages with Respect to 0V, GND = 0V)
Symbol Parameter Ambient temperature (Power applied) Storage temperature Voltage on any pin (except X1) Voltage on X1 pin VCC VC3 AVC3 Supply voltage Core supply voltage Supply voltage Maximum IOL per I/O pin Min -40 -65 -0.5 -0.5 -0.5 -0.5 -0.5 Typ Max +85 +150 VCC + 0.5 VC3 + 0.5 6.5 4.5 4.5 10 Unit C C V V V V V mA
Recommended Operating Conditions
Table 4. Recommended Operating Conditions
Symbol VCC VC3 AVC3 tA Parameter Supply voltage (I/O) Supply voltage (Core) Supply voltage (Analog) Operating ambient temperature Min 3 3 3 0 Typ 3.3/5.0 3.3 3.3 Max 5.5 3.6 3.6 70 Unit V V V C
DC Characteristics
Table 5. DC Characteristics (TA = 25C, VCC = 5V 10%, VC3 = 3.3V 10%)
Symbol VIL VIH VOL VOH ICC Core ICC I/O Parameter Low-level input voltage High-level input voltage Low-level output voltage at IOL = 3.2 mA(1) High-level output voltage at IOH = -0.8 mA (2) Power supply current (Crystal frequency = 11.2896 MHz) Power down supply current Notes: 1. IOL: Low-level output current. 2. IOH: High-level output current. VCC 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 2.8 4.5 60 20 1 80 30 2 Min -0.5 -0.5 2.3 3.3 3 Typ Max 1.0 1.7 VCC + 0.5 VCC + 0.5 0.45 0.45 Unit V V V V mA A
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Product Overview
The SAM9753 is part of a new generation of integrated solutions for electronic musical instruments. The device includes all key circuitry on a single silicon chip: sound synthesizer/processor, 16-bit control processor, interface with keyboards, switches, sliders, LEDs, LCD display, etc. The synthesis/sound processing core of the SAM9753 is taken from the SAM97xx series, the quality of which has already been demonstrated through dozens of different musical products: electronic pianos, home keyboards, professional keyboards, classical organs and sound expanders. The maximum polyphony is 64 voices without effects. A typical application is 38-voice polyphony with reverb, chorus, 4-band equalizer and surround. The SAM9753 is directly compatible with most available musical keyboards. This includes configuration options for spring- or rubber-type contacts and for common anode- or common cathode-type matrices. A 64 s timing accuracy for velocity detection provides a very reliable dynamic response even with low-cost unweighted keyboards. The time between contacts is coded with 256 steps on a logarithmic time scale, then converted by software to a 128-step MIDI scale according to the type of keyboard and selected keyboard sensitivity. The SAM9753 can handle directly up to 176 switches. Switches, organized in matrix form, require only a serial diode. Up to 88 LEDs can be directly controlled by the SAM9753 in a time-multiplexed way. Additional LEDs can be connected through additional external shift registers using the GPIO lines (general-purpose I/O lines) of the SAM9753. The built-in analog-to-digital converter of the SAM9753 allows connection of continuous controllers like pitch-bend wheel, modulation, volume sliders, tempo sliders, etc. Up to 16 sliders can be connected. The SAM9753 can be directly connected to most LCD displays through an 8-bit dedicated data bus and three control signals. Configuration options allow the SAM9753 to cover a wide range of musical products, from the lowest-cost keyboard to the high-range digital piano, thanks to flexible memory and I/O organization: built-in 64K bytes of RAM and up to 32M bytes of external memory for firmware, orchestration and PCM data. The external memory can be ROM, RAM or Flash. Memory types can be mixed, but for most applications there is no need for external RAM memory as the built-in 64K bytes of RAM is enough to handle firmware variables and reverb delay lines. External Flash memory can be programmed on-board from a host processor through the SAM9753. The SAM9753 operates from a single 11.2896 MHz crystal. A built-in PLL raises the frequency to 45.2 MHz for internal processing. This allows radio frequency interference (RFI) to be minimized, making it easier to comply with FCC, CSA and CE standards. A power-down feature is also included which can be controlled externally (PDWN pin). This makes the SAM9753 very suitable for battery-operated instruments. The SAM9753 was designed with a rapid time-to-market in mind. The SAM9753 product development program includes key features to minimize product development efforts: * * * * * * Specialized debug interface, allowing on-target software development with a source code "CodeView" debugger Standard sound generation/processing firmware Standard orchestration firmware Windows(R) tools for sounds, soundbanks and orchestration developments Standard soundbanks Strong technical support available directly from Dream(R)
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Architectural Overview
The highly integrated architecture from SAM9753 combines a specialized high-performance RISC-based digital signal processor (DSP) and a general-purpose 16-bit CISCbased control processor (P16). An on-chip memory management unit (MMU) allows the DSP and the control processor to share an internal 32K x 16 RAM as well as external ROM and/or RAM memory devices. An intelligent peripheral I/O interface function handles other I/O interfaces, such as the on-chip MIDI UART and three timers, with minimum intervention from the control processor. A keyboard/switches/sliders/LEDs autonomous scanning interface handles the specific musical instrument peripherals, including accurate keyboard velocity detection and communicates with the control processor through a dedicated 128 x 16 dual-port RAM. An LCD display interface allows direct connection to common LCD displays. The DSP engine operates on a frame-timing basis with the frame subdivided into 64 process slots. Each process is itself divided into 16 micro-instructions known as algorithms. Up to 32 DSP algorithms can be stored on-chip in the Alg RAM memory, allowing the device to be programmed for a number of audio signal generation/processing applications. The DSP engine is capable of generating 64 simultaneous voices using algorithms such as wavetable synthesis with interpolation, alternate loop and 24 dB resonant filtering for each voice. Slots may be linked together (ML RAM) to allow implementation of more complex synthesis algorithms. A typical musical instrument application will use a little more than half the capacity of the DSP engine for synthesis, thus providing state-of-the-art 38-voice synthesis polyphony. The remaining processing power may be used for typical functions such as reverberation, chorus, surround effect, equalizer, etc. Frequently-accessed DSP parameter data are stored into five banks of on-chip RAM memory. Sample data or delay lines that are accessed relatively infrequently are stored in external ROM, or in the built-in 32K x 16 RAM. The combination of localized microprogram memory and localized parameter data allows micro-instructions to execute in 22 ns (45 MIPS). Separate buses from each of the on-chip parameter RAM memory banks allow highly parallel data movement to increase the effectiveness of each microinstruction. With this architecture, a single micro-instruction can accomplish up to six simultaneous operations (add, multiply, load, store, etc.), providing a potential throughput of 270 million operations per second (MOPS).
DSP Engine
P16 Control Processor and I/O Functions
The P16 control processor is a general-purpose 16-bit CISC processor core, which runs from external memory. A debug ROM is included on-chip for easy development of firmware directly on the target system. This ROM also contains the necessary code to directly program externally connected Flash memory. The P16 includes 256 words of local RAM data memory for use as registers, scratchpad data and stack. The P16 control processor writes to the parameter RAM blocks within the DSP core in order to control the synthesis process. In a typical application, the P16 control processor parses and interprets incoming commands from the MIDI UART or from the scanning interface and then controls the DSP by writing into the parameter RAM banks in the DSP core. Slowly changing synthesis functions, such as LFOs, are implemented in the P16 control processor by periodically updating the DSP parameter RAM variables. The P16 control processor interfaces with other peripheral devices, such as the system control and status registers, the on-chip MIDI UART, the on-chip timers and the scanning interface through specialized "intelligent" peripheral I/O logic. This I/O logic
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automates many of the system I/O transfers to minimize the amount of overhead processing required from the P16.
Memory Management Unit (MMU)
The Memory Management Unit (MMU) block allows external ROM and/or RAM memory resources to be shared between the synthesis/DSP and the P16 control processor. This allows a single ROM device to serve as sample memory storage for the DSP and as program storage for the P16 control processor. An internal 32K x 16 RAM is also connected to the MMU, allowing RAM resources to be shared between the DSP for delay lines and the P16 for program data. The scanning interface consists of hardwired logic. It time-multiplexes keyboards, switches and LED connections, thus minimizing the amount of wiring required. It communicates with the P16 through an 128 x 16 dual-port RAM and a few control registers. When a new incoming event is detected, such as key-on, key-off or switch change, the scanning interface will notify the P16 by indicating the type of event. The P16 then simply reads the dual-port RAM to get the corresponding parameter, such as velocity or switch status. Conversely, the P16 simply writes into the dual-port RAM the LED states to be displayed and the scanning interface will then take care of time-multiplexing the display. The scanning interface uses an unique key velocity detect scheme with a pseudo-logarithmic time scale. This allows velocities to be accurately detected, even when keyboard keys are pressed very softly. Finally, a built-in 8-bit analog-to-digital converter (ADC) allows the connection of up to 16 continuous controllers through external analog multiplexers such as the 4051.
Scanning Interface
LCD Display Interface
The LCD display interface uses a dedicated bi-directional data bus (DB0 - DB7), an instruction/data control (RS), a read/write signal (R/W) and an enable signal (E). Built-in features are included to accommodate even the slowest LCD displays. The SAM9753 enables Flash memory programming in three different ways: * * Blank Flash programming is done by the debug interface. This mode is very slow and should be reserved for the initial boot sector programming. Program update. All the Flash content can be re-programmed. The SAM9753 cannot play music during the Flash erase and programming. A specific firmware is used to program Flash with the DSP. Parameter update, e.g., in keyboard applications, backup parameter and sequencer song. If the Flash enables concurrent read while program/erase, it is possible to backup parameters in the upper memory plane while the microprocessor firmware is running on the lower plane. The SAM9753 cannot play music during the parameter backup because sound samples are stored in both memory planes. 3.3V or 5V: In case of 3.3V, the I/O voltage VCC should be supplied by 3.3V and all the external components (MIDI, DAC, ...) should be 3.3V Access time: 100 ns (for 11.2896 MHz crystal) Bottom boot Dual plane with concurrent read while program/erase recommended for parameters backup
Flash Programming
*
Flash Features
* * * *
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Timing Diagrams
All timings are relative to 11.2896 MHz crystal between X1 and X2. Figure 3. Scanning (Keyboard, Switches, LEDs and Sliders) Timing Diagram
tKBD tSCLK SCLK KBDIO ROW BR[0:10] tIO
tKA tKD
tIOA tIOD
MK[0:10]
tKA tKD
tIOG
tIOH
VIN
tVA tVD
Table 6. Scanning Timing Parameters
Symbol tKBD tIO tSCLK tKA tKD tIOA tIOD tIOG tIOH tVA tVD Parameter Keyboard access (KBDIO high time) Switches/leds access (KBDIO low time) Internal scanning clock period Break (contact1) and Make (contact2) data from keyboard valid from rising KBDIO Break (contact1) and Make (contact2) data from Keyboard floating from rising KBDIO Switch data valid from falling KBDIO Switch data floating from falling KBDIO LED data MK guard time LED data floating from rising KBDIO Analog VIN sample start time from ROW change (Start sample and hold voltage follow mode) Analog VIN sample end time from ROW change (Switch to hold mode) 4.1 177 0 1 2.2 1.3 Min Typ 1.4 4.3 354 1.2 1.6 4 4.4 27 88 Max Unit s s ns s s s s ns ns s s
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Figure 4. External ROM, RAM, I/O Timing Diagram
CS0 CS1 tCSDV tRWHCSH
RD WR D0 - D15
tRW tRWDV tAVDV tRWHADX
tRWDX
A0 - A23
Table 7. External ROM, RAM, I/O Timing Parameters
Symbol tCSDV tRWDV tAVDV tRW tRWHCSH tRWHADX tRWDX Parameter Access time from CSx low Access time from RD, WR low Access time from address valid RD, WR pulse width CSx high from rising RD or WR Address valid after rising RD or WR Data hold time from rising RD or WR 10 10 10 Min 106 61 106 89 Typ Max Unit ns ns ns ns ns ns ns
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Figure 5. Digital Audio Timing Diagram
tCW tCW WSBD tCLBD
CLBD tSOD DABDX DAAD tSOD
Table 8. Digital Audio Timing Parameters
Symbol tCW tSOD tCLBD Parameter CLBD rising to WSBD change DABDx valid prior to/after CLBD rising CLBD cycle time Min 167 167 354 Typ Max Unit ns ns ns
Figure 6. Digital Audio Frame
WSBD (I 2S) WSBD (Japanese) CLBD
DABDx DAAD MSB LSB (16 Bits
000 00 0 00 00 0 0 MSB LSB (20 Bits) LSB (18 Bits)
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Crystal Compensation and LFT Filter
Figure 7. Recommended Crystal Compensation and LFT Filter (1), (2), (3), (4)
X1 98 X1
99 C4 22 pF C1 22 pF C2 2.2 nF C3 10 nF R1 100 100
X2
LFT
GND
Notes:
1. All GND pins should be connected to GND plane below IC. 2. All VCC pins should be connected to VCC plane below IC. 3. X1, C1, C2, C3, C4, R1 connections should be short and shielded. The GND return from C1, C4, C3, should be the GND plane from SAM9753. 4. 0.1 F decoupling caps should be placed at each corner of the IC. An additional 10 F capacitor should be placed close to X1.
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Reference Design
Figure 8. Typical Keyboard, Switch, LED and Slider Connections
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SAM9753 Operation
The reader is assumed to be familiar with the functioning of the SAM97xx series. Refer to the SAM9707 product development kit "prgdvkit.pdf" document. This document can be obtained under special conditions from Atmel. This section describes operation and registers specific to SAM9753.
Memory Mapping
Table 9. Memory Mapping
Size (in words) 256 768 32M - 1K 32K 4K 4K 216K 32M - 256K Address Low 000:0000 000:0100 000:0400 200:0000 200:8000 200:9000 200:A000 204:0000 Address High 000:00FF 000:03FF 1FF:FFFF 200:7FFF 200:8FFF 200:9FFF 203:FFFF 2FF:FFFF Access SAM97xx standard routine ROM Built in debug ROM External ROM/Flash (WCS0) Built in SRAM External memory page XIO0 (XIO0) External memory page XIO1 (XIO1) Not used External SRAM (WCS1)
I/O Mapping
The I/O Mapping Table refers to the SAM9707 product development kit "prgdvkit.pdf" available from Atmel. Table 10. I/O Mapping
Write 00 - 09 0A 0B 0C - 0E 0F Read 00 - 09 0A X 0C - 0E 0F Access Standard SAM97xx I/O (Refer to prgdvkit.pdf) LCD port Keyboard configuration Scanning port ADD0 - 2 GPIO control/status
LCD Interface
The SAM9753 can be directly connected to most LCD displays. The SAM9753 provides an 8-bit data bus (DB0 - DB7) and three output control pins RS, RW and ENB. All the LCD pins are controlled by I/O access ADD OAH. The I/O reads only the 8-bit data bus. The I/O writes into the 11-bit LCD_Reg. Refer to Table 11 and Table 12. Table 11. LCD Interface
LCD_Reg[7:0] LCD_Reg[8] LCD_Reg[9] LCD_Reg[10] DB[7:0] RS RW ENB
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Table 12. LCD Interface
I/O Access Write Write Read Read I/O Data IOD[10:0] (IOD[9]=0) IOD[10:0] (IOD[9]=1) xx xxx, LCD_D[7:0] LCD_Reg[10:0] IOD[10:0] LCD_Reg[9]=0 IOD[10:0] LCD_Reg[9]=1 LCD_Reg[9]=0 LCD_Reg[9]=1 DB[7:0] IOD[7:0] output LCD_D[7:0] input LCD_Reg[7:0] output LCD_D[7:0] input R/W 0 1 0 1 Set LCD in write mode Set LCD in read mode Invalid read from LCD in write mode Read from LCD
Keyboard Configuration Register
The configuration register allows the user to work with a variety of keyboards. This writeonly 2-bit register is mapped to the address OBH in the I/O space. Reg[0] = contact type 0 for rubber type contact 1 for spring type contact Reg[1] = diode wiring 0 for common anode wiring 1 for common cathode wiring The default configuration (power-up) is common anode (Reg[1] = 0) and rubber contact (Reg[0] = 0) which corresponds to most popular keyboards.
Scanning Interface
The SAM9753 has built-in specialized hardware that allows the following functions: * * * * Scanning of up to 88 keys from an external keyboard, with key-on and key-off velocity measurement (time between contacts) Scanning of up to 176 switches Time multiplex control of up to 88 LEDs Analog-to-digital conversion of up to 16 analog sources
The P16 interfaces with the scanning using a three-address port located at 0CH to 0EH in the I/O mapping. This port enables access to the keyboard RAM. This 128 x 11 RAM is mapped as shown in Table 13. Table 13. Keyboard RAM Mapping
Address 00H to 57H 58H to 5FH 60H to 6FH 70H to 7FH Content Key velocity and status LED data Switch status ADC value
Keyboard Status
(I/O address OCH read-only) D[7] KRQ flag = 1 indicates that a key-on or key-off has been detected and that the P16 service is requested. This flag is automatically cleared by writing to data H for the detected key.
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D[6:0] specifies which keyboard key is requesting the service, valid only if KRQ flag = 1. Key number ranges from 0 to 87. RAM Address (I/O address OCH write-only) D[6:0] RAM address css D[7] don't care Table 14. RAM Address
Address 00H to 57H 58H to 5FH 60H to 6FH 70H to 7FH Index 8*i + ROW[2:0] ROW[2:0] ROW[3:0] ROW[3:0] Content Key velocity and status LED data Switch status ADC value
"i" refers to the MKi or BRi signal number that ranges from 0 to 10. For example, the information regarding the key at ROW3, column MK5/BR5, is found at RAM address 8*5+3 = 43. The scanning hardware cycles the ROW[2:0] signals from 0 to 7 to the output pins in 45 s (5.7 s per row). If the alternate function ROW3 is not used, then the switch status and ADC value information are aliased (data from 68H to 6FH = data from 60H to 6FH, data from 78H to 7FH = data from 70H to 77H).
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RAM Data DataL[7:0] DataH[2:0] DataH[7:3] Table 15. Scanning RAM Data Format
Bit 10 Key Velocity and Status LED Data Switch Data ADC Status SRQ MK10 BR10 X 9 ON MK9 BR9 X 8 BUSY MK8 BR8 X MK7 BR7 MK6 BR6 MK5 BR5 MK4 BR4 7 6 5 4 3 TIME MK3 BR3 MK2 BR2 MK1 BR1 MK0 BR0 2 1 0
I/O address ODH, Data[7:0] I/O address OEH, Data[10:8] don't care
ADC DATA
*
Key Velocity and Status: - SRQ: If 1, indicates that the velocity detection is complete and that this key requests attention from the P16. In this case BUSY = 0, ON and TIME hold valid information. ON: 1 indicates key-on, 0 indicates key-off. Valid only if SRQ = 1. BUSY: Used internally by the scanning hardware, indicates "velocity detection in progress". TIME: From 0 to 255, valid only if SRQ = 1, indicates the time between contacts in multiples of 45 s. Set to 255 if the time is greater or equal to 256*45 s.
- - -
* * *
LED Data: The P16 should write to these locations the MK information which should appear to the MK[10:0] pins at ROW[2:0] time. Switch Data: These fields hold the BR information read from the BR[10:0] pins at ROW[3:0] time. ADC Status: These fields represent the analog voltage at VIN pin at ROW[3:0] time, from 0 (VIN = VREFN) to 0FFH (VIN = VREFP).
19
1774C-DRMSD-06/02
GPIO
The pins GPIO[3:0] in normal mode are controlled by the SAM97xx configuration and control/status registers (refer to prgdvkit.pdf). The SAM9753 additional GPIO control/status register controls GPIO[3:0] alternate mode and GPIO4 normal and alternate mode. The GPIO register is located at address 0xF in the I/O mapping. Table 16. GPIO Mapping
Data Bit Number 7 6 5 4 3 2 1 0 Write x GPIO4 OE/ GPIO1 Alt GPIO0 Alt GPIO4 Data GPIO4 Alt data (DBOUT) GPIO3 Alt data (DBACK) GPIO4 Alt OE/ Read x x x x Debug/pin GPIO4 pin (DBIN) GPIO Reg[1] (DBACK) GPIO2 pin (DBCLK)
Table 17. GPIO0
Normal Input Mode SAM97xx_config_Reg[0] (I/O add0) SAM9753_GPIO_Reg[4] (I/O addF) Note: 0 x Normal Output Mode 1 0 Alt Output Mode(1) 1 1
1. In alternate output mode, GPIO0 = ROW3. Refer to description of pins ROW0 - ROW2 in Table 1.
Table 18. GPIO1
Normal Input Mode SAM97xx_config_Reg[1] SAM9753_GPIO_Reg[5] Note: 0 x Normal Output Mode 1 0 Alt Output Mode(1) 1 1
1. In alternate output mode, GPIO1 = WCS1. Refer to description of pin WCS1 in Table 1.
Table 19. GPIO2
Normal Input Mode SAM97xx_config_Reg[2] DEBUG Pin Note: 0 1 Normal Output Mode 1 1 Alt Output Mode(1) x 0
1. In alternate output mode, GPIO2 is configured as input and assumed as DBCLK (SAM9753_GPIO[0]).
20
SAM9753
1774C-DRMSD-06/02
SAM9753
Table 20. GPIO3
Normal Input Mode SAM97xx_config_Reg[3] DEBUG Pin Note: 0 1 Normal Output Mode 1 1 Alt Output Mode(1) x 0
1. In alternate output mode, GPIO3 is configured as output and GPIO3 = DBACK (SAM9753_GPIO_reg[1]).
Table 21. GPIO4
Normal Input Mode SAM9753_GPIO_Reg[6] SAM9753_GPIO_Reg[0] DEBUG Pin Note: 0 x 1 Normal Output Mode 1 x 1 Alt Output Mode(1) x 0 0 Alt Output Mode(1) x 1 0
1. In alternate mode, GPIO4 is used for serial debug data: In input, SAM9753_GPIO[2] (DBIN) = GPIO4 In output, GPIO4 = SAM9753_GPIO_Reg[2] (DBOUT).
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1774C-DRMSD-06/02
Mechanical Dimensions
Figure 9. 144-lead TQFP Package Drawing
Table 22. 144-lead TQFP Package Dimensions (in millimeters)
Min A A1 A2 D D1 E E1 L P B 0.17 1.40 0.05 1.35 21.90 19.90 21.90 19.90 0.45 Nom 1.50 0.10 1.40 22.00 20.00 22.00 20.00 0.60 0.50 0.22 0.27 Max 1.60 0.15 1.45 22.10 20.10 22.10 20.10 0.75
22
SAM9753
1774C-DRMSD-06/02
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1774C-DRMSD-06/02 0M

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